Central processing unit

Results: 2609



#Item
941Bulk Disambiguation of Speculative Threads in Multiprocessors Luis Ceze, James Tuck, C!lin Ca

Bulk Disambiguation of Speculative Threads in Multiprocessors Luis Ceze, James Tuck, C!lin Ca"caval! and Josep Torrellas University of Illinois at Urbana-Champaign !IBM Research

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2006-07-06 01:16:16
942Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System ∗  Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King and Josep Torrellas

Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System ∗ Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King and Josep Torrellas

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2009-05-31 00:24:02
943Report No. UIUCDCS-R[removed]UILU-ENG[removed]A Brief Description of the NMP ISA and Benchmarks

Report No. UIUCDCS-R[removed]UILU-ENG[removed]A Brief Description of the NMP ISA and Benchmarks

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2005-10-16 18:16:47
944OpenSPARC – An Open Platform for Hardware Reliability Experimentation Ishwar Parulkar and Alan Wood Sun Microsystems, Inc. James C. Hoe and Babak Falsafi Carnegie Mellon University

OpenSPARC – An Open Platform for Hardware Reliability Experimentation Ishwar Parulkar and Alan Wood Sun Microsystems, Inc. James C. Hoe and Babak Falsafi Carnegie Mellon University

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2010-12-23 23:46:10
945Managing Multiple Low-Power Adaptation Techniques: The Positional Approach Michael C. Huang, University of Rochester Jose Renau and Josep Torrellas, University of Illinois at Urbana-Champaign Decision: What to adapt Stat

Managing Multiple Low-Power Adaptation Techniques: The Positional Approach Michael C. Huang, University of Rochester Jose Renau and Josep Torrellas, University of Illinois at Urbana-Champaign Decision: What to adapt Stat

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2003-11-23 14:36:32
946Alpha[removed]Microprocessor Data Sheet Order Number: EC–QP98C–TE Revision/Update Information: This is a revised manual. It supersedes

Alpha[removed]Microprocessor Data Sheet Order Number: EC–QP98C–TE Revision/Update Information: This is a revised manual. It supersedes

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Source URL: download.majix.org

Language: English - Date: 2013-01-10 05:04:38
947Alpha[removed]Microprocessor Data Sheet Order Number: EC–QAEPD–TE Revision/Update Information:  Digital Equipment Corporation

Alpha[removed]Microprocessor Data Sheet Order Number: EC–QAEPD–TE Revision/Update Information: Digital Equipment Corporation

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Source URL: download.majix.org

Language: English - Date: 2013-01-10 05:03:36
948Microsoft PowerPoint - present_isca03_2 [Compatibility Mode]

Microsoft PowerPoint - present_isca03_2 [Compatibility Mode]

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2010-12-24 19:17:44
949Learning Outcomes Processes and Threads Implementation • An understanding of the typical implementation strategies of processes and threads

Learning Outcomes Processes and Threads Implementation • An understanding of the typical implementation strategies of processes and threads

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Source URL: cgi.cse.unsw.edu.au

Language: English - Date: 2015-03-30 21:24:57
950Facelift: Hiding and Slowing Down Aging in Multicores∗ Abhishek Tiwari and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract

Facelift: Hiding and Slowing Down Aging in Multicores∗ Abhishek Tiwari and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2008-09-13 00:18:06